PX14400 – 400 MS/s, 14 bit, 2 Channel, PCIe x8, Xilinx Virtex-5 FPGA, Digitizer Board
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PX14400 Features

- 2 Analog Channels at up to 400 MHz Sample Rate per Channel
- 14 Bits of A/D Resolution
- Bandwidth from 100 KHz to 400 MHz
- 1 Gigabyte of On-Board Memory
- Over 1200 MB/s Continuous Transfer Over PCI Express Bus (8 lanes)
- Optional Customizable Xilinx Virtex-5 FPGAs
- Optional 10/100/1000 Ethernet Port
The PX14400 is a dual channel waveform capture board that provides a remarkable combination of high speed and high resolution sampling along with a very large memory capacity. Signal frequencies up to 200 MHz can be accurately captured when using the programmable gain amplifier or up to 400 MHz if the direct transformer coupled connection is used.
The entire 1 GB memory may be used as an exceptionally large FIFO for acquiring non-stop, continuous data directly to either the PCI Express (PCIe) bus or the SAB. In Buffered Acquisition Mode (where the 1 GB RAM FIFO is used) the PX14400 is capable of sustaining the full 1600 megabyte/sec data rate over the SAB or 1200 MB/s over the PCIe bus. Significant test data has shown that recording with large FIFO buffering can be continuous at these rates even when operating in traditional non real-time environments such as the Windows operating system.
The PX14400 employs up to two Virtex-5 FPGAs, where one of the FPGAs is available as an option for customers to implement their own custom in-line signal processing. A standard FIFO interface to the Signatec specific logic portion of the PX14400 along with control flags, an example program using the FIFOs/flags and a programmer’s manual are provided with the optionally available PX14400 Firmware development kit.
The PX14400 can be ordered either with or without this 2nd user accessible FPGA. Boards without the FPGA are –DR versions of the product (data recording only) and boards with the user FPGA are –SP versions of the product (signal processing).
The PX14400 was designed to maximize the quality of the captured signal in terms of signal-to-noise ratio and spurious-free dynamic range over a very wide frequency range. The programmable amplifier allows for setting the full scale input voltage from 200 millivolts to 3.0 volts in 1 dB steps.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 58 to 400 MHz, offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
Up to five PX14400 boards may be interconnected in a Master/Slave configuration via a ribbon cable that connects at the top of the board. In this configuration the clock and trigger signals from the Master drive the Slave boards synchronize sampling across all boards. Additional boards can be synchronized, even across computer chassis, when using Signatec’s SYNC1500-6 product. The PX14400 supports single shot, segmented, and pretrigger triggering modes.
Product Specifications
Specification Data Sheet Revision 1.00 – 09/29/2009
| External Signal Connections | |
| Analog Input, Channel 1: | SMA |
| Analog Input, Channel 2: | SMA |
| Clock Input: | SMA |
| Trigger Input: | SMA |
| Digital Input / Output: | SMA |
| Analog Inputs – Amplifier | |
| Full Scale Voltage Ranges: | 200 mV to 3.0 V in 1dB steps |
| Impedance: | 50 ohms |
| Bandwidth: | 100kHz - 200 MHz (Bessel filter) |
| SNR (1-200 MHz): | 65 dB |
| SFDR (@ 100 MHz): | 83 dB |
| Analog Inputs – Transformer | |
| Full Scale Voltage Ranges: | 1.1 Volts |
| Impedance: | 50 ohms |
| Bandwidth: | 500 kHz to 400 MHz |
| SNR (1-200 MHz): | 70 dB |
| SFDR (@ 100 MHz): | 83 dB |
| External Trigger | |
| Signal Type: | digital, TTL signal level |
| Impedance: | >10k ohms |
| Bandwidth: | 50 MHz |
| Internal Synthesized Clock | |
| Frequency Range: | 58.0 - 400 MHz |
| Resolution: | better than 10 PPM |
| Accuracy: | better than 5 PPM |
| Unsettable Ranges: | 277-308 MHz |
| External Clock | |
| Signal Type: | sine wave or square wave |
| Coupling: | AC |
| Impedance: | 50 ohms |
| Frequency: | 20 MHz to 400 MHz |
| Amplitude: | 100 mV p-p to 2.0 V p-p |
| Post ADC Clock Divider | |
| Divider Settings: | 1, 2, 4, 8, 16, 32 |
| Reference Clock | |
| Internal: | 10.0 MHz, +/- 5 ppm max. |
| External: | 10.0 MHz, +/- 50 ppm max (required for lock) |
| Digital Input / Output | |
| Type: | TTL Logic Level (standard) |
| Max. Frequency: | 200 MHz |
| Connection: | 50 ohms to FPGA I/O |
| Trigger Modes | |
| Post Trigger: | single start trigger fills active memory |
| Pretrigger: | single trigger stops acquisition |
| Segmented: | start trigger for each memory segment |
| Trigger Options | |
| Pretrigger Samples: | samples prior to trigger are stored; Single Channel: 8k max.; Dual Channel: 4k max per channel |
| Delayed Trigger: | delay from trigger to data storage; Up to 64k digitizer clock cycles |
| Memory | |
| Total Size: | 512 Megasamples |
| Segment Size: | Up to 128 Megasamples |
| Segment Re-Arm Time: | 150 nanoseconds |
| Addressing: | DMA transfers from starting address |
| Signatec Auxiliary Bus (Version 4) | |
| Data Transfer Rates: | up to 2000 MB/s max @ 64 bits |
| Data Direction: | Output only |
| Power Requirements | |
| +12V: | 1.0 Amps max. |
| +3.3V: | 3.3 Amps max. |
| Absolute Maximum Ratings | |
| Analog Inputs: | +/- 4 volts |
| Trigger Input: | -0.2 to +4.0 volts DC |
| Clock Input: | 5 volts peak to peak |
| Ambient Temperature: | 0 to 50C |

