PX14400A – 400 MS/s, 14 bit, AC Coupled, 2 Channel, Xilinx Virtex-5 FPGA, PCIe x8, High Speed Digitizer Board

The PX14400A is a dual channel AC-coupled waveform capture board that can acquire up to 400 MS/s on each channel with 14-bit resolution. (For DC-coupled requirements, refer to PX14400D or PX14400D2 product models.) The PX14400A analog front end is hardware configured to use a programmable gain amplifier with a signal frequency capture range of 100 kHz to 200 MHz, or a direct transformer coupled connection with a signal frequency capture range of 500 kHz to 400 MHz.

The PX14400A is designed to maximize the quality of the captured signal in terms of signal-to-noise ratio and spurious-free dynamic range over a very wide frequency range. The programmable amplifier allows for software selectable setting of the full scale input voltage range from 220 millivolts to 3.5 volts peak-to-peak in 1 dB steps. The transformer coupled connection has a single fixed full scale input voltage range of 1.1 volts peak-to-peak.

A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 20 MHz to 400 MHz (except for an un-settable range of 277 MHz to 308 MHz), offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, ±5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.

The PX14400A has a primary sample-data RAM bank of 512 MB memory for onboard sample data storage. Alternatively, PCIe Buffered Acquisition mode utilizes the onboard RAM as a FIFO to provide non-stop continuous acquisition and streaming of sample data to the host PC via the PCIe interface. With PCIe Buffered Acquisition mode, the PX14400A can sustain up to a maximum 1.4 GB/s data streaming rate over its PCIe Gen1 x8 interface to the host PC for real-time high-speed processing and/or data recordings.

The PX14400A also provides an option for an onboard secondary Xilinx Virtex-5 SX50T or SX95T FPGA with its own 512 MB RAM bank for dedicated embedded signal processing. FPGA processing models of the PX14400A include DDC, FFT, and FIR Filter features standard. The processing FPGA is fully end user programmable, allowing for custom developed embedded processing routines.

Up to five PX14400A digitizers can be setup for synchronous acquisition operations for a total of 10 input channels by utilizing the separate Signatec SYNC1500 clock/trigger driver source card.

A Windows oscilloscope program, the PX14400 Scope App, allows the operator to view/edit all digitizer hardware settings as well as record and display acquisition data. It is included along with a full complete C SDK for custom application development.

Product Specifications

Product: PX14400A (AC-Coupled) Full Data Sheet
Update: Revision 1.5 - 08/24/2015
File Size: 770 KB

External Signal Connections
     Analog Input, Channel 1: SMA
     Analog Input, Channel 2: SMA
     Clock Input: SMA
     Trigger Input: SMA
     Digital Input / Output: SMA
Analog Inputs – Amplifier Front End
     Full Scale Voltage Ranges: 200mV to 3.5V peak-to-peak (in 1dB increments)
     Impedance: 50 ohms
     Bandwidth: 100 kHz - 200 MHz (Bessel filter)
     Coupling: AC
     SNR (1-200 MHz): 65 dB
     SFDR (@ 100 MHz): 83 dB
Analog Inputs – Transformer Front End
     Full Scale Voltage Ranges: 1.1V peak-to-peak
     Impedance: 50 ohms
     Bandwidth: 500 kHz to 400 MHz
     SNR (1-200 MHz): 68 dB
     SFDR (@ 100 MHz): 80 dB
External Trigger
     Signal Type: digital, LVCMOS signal level
     Impedance: >10k ohms
     Bandwidth: 50 MHz
Internal Synthesized Clock
     Frequency Range: 20 MHz to 400 MHz
     Unsettable Ranges: 277 MHz to 308 MHz
     Resolution: better than ±10 PPM
     Accuracy: better than ±5 PPM
External Clock
     Signal Type: sine wave or square wave
     Coupling: AC
     Impedance: 50 ohms
     Frequency: 20 MHz to 400 MHz
     Amplitude: 100mV to 2V peak-to-peak
     Clock Dividers: 1 to 20
Post ADC Clock Divider
     Divider Settings: 1, 2, 4, 8, 16, 32
Reference Clock
     Internal: 10.0 MHz, ±5 PPM max.
     External: 10.0 MHz, ±50 PPM max (required for lock)
Digital Input / Output
     Type: TTL Logic Level (standard)
     Max. Frequency: 200 MHz
     Connection: 50 ohms to FPGA I/O
     Output Modes: 0V, Synchronized Trigger, ADC Clock ÷ 2, 3.3V
     Input Modes: Digital pulse for timestamp request
Trigger Modes
     Post Trigger: single start trigger fills active memory
     Segmented: start trigger for each memory segment
Trigger Options
     Pre-trigger Samples: samples prior to trigger are stored; Single Channel: 8k max.; Dual Channel: 4k max per channel
     Trigger Delay Samples: delay from trigger to data storage; Up to 64k digitizer clock cycles
     Total Size for Acquisition: 256 Megasamples (512 MB)
     Segment Size: Up to 128 Megasamples
     Segment Re-Arm Time: 150 nanoseconds
     Addressing: DMA transfers from starting address
Power Requirements
     +3.3V: 3.3 Amps max.
     +12V: 1.0 Amps max.
Absolute Maximum Ratings
     Analog Inputs: ±4V
     Trigger Input: -0.2V to +4V DC
     Clock Input: 5V peak-to-peak
     Operating Temperature: +32 to +122F / 0 to +50C
     Storage Temperature: -4 to +158F / -20 to +70C
     Operating Relative Humidity: 10% to 90%, non-condensing
     Operating Vibration: 0.25 G, 5 Hz to 500 Hz
     Operating Shock: 2.5 G, 11 ms, 1/2 sine
     Board Dimensions: 7.5" L x 4.3" H x 0.75" W /
190.5 mm L x 109.22 mm H x 19.05 mm W