PX1500-4 – 1.5 GS/s 4 Channel or 3.0 GS/s 2 Channel, 8 bit, PCIe x8, Xilinx Virtex-5 FPGA, Digitizer Board
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PX1500-4 Features

- 4 Analog Channels at up to 1.5 GHz Sample Rate per Channel
- 2 Analog Channels at up to 3.0 GHz Sample Rate per Channel in Interleaved Mode
- 8 Bits of A/D Resolution
- Bandwidth from 5 MHz to 2 GHz
- 2 Gigabytes of On-Board Memory
- 1400 MB/s Continuous Transfer Over PCI Express Bus (8 lanes)
- Optional Customizable Xilinx Virtex-5 FPGAs
The PX1500-4 is a four channel waveform capture board that can acquire up to 1500 MSPS on each channel or up to 3000 MSPS for dual channel operation when ADC data is interleaved. The PX1500-4 can be set up to use either a transformer coupled front end or an amplifier connection. The transformer connection can only be set for AC coupled operation and has a frequency capture range of 5 MHz to 2 GHz. The amplifier can be set for either AC or DC coupled operation with a frequency range of up to 1 GHz.
The board features an 8 lane PCI Express connection to the computer host as well as 2 gigabytes of on-board memory. If the average acquisition data rate does not exceed 1400 MB/s then the entire 2 GB memory may be used as an exceptionally large FIFO for acquiring non-stop, continuous data directly to the PCI Express bus. Significant test data has shown that recording with large FIFO buffering can be continuous at these rates even when operating in traditional non real-time environments such as the Windows operating system.
The PX1500-4 employs two Virtex-5 FPGAs which have ample unused programmable logic cells for customers to implement their own custom in-line signal processing (as an option). Hooks and examples are provided to simplify this task.
The PX1500-4 was designed to maximize the quality of the captured signal in terms of signal-to-noise ratio and spurious-free dynamic range over a very wide frequency range. For this reason, there are no switch components in the analog signal path or bandwidth limiting programmable gain amplifiers; giving customers the benefit of a nearly direct path to the ADC from either the amplifier or transformer coupled input.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 200 MHz, the minimum allowable ADC clock, to 1500 MHz, offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
Up to two PX1500-4 boards may be interconnected in a Master/Slave configuration via a ribbon cable that connects at the top of the board. In this configuration the clock and trigger signals from the Master drive the Slave boards so that data sampling on all boards occurs simultaneously up to 500MHz. Up to six boards can be set up for fully synchronized operation up to 1.5GHz by utilizing the SYNC1500-6 as the clock and trigger source for the system.
Product Specifications
Product: PX1500-4 Full Data Sheet
Update: Revision 1.07 - 09/25/2012
File Size: 688 KB
| External Signal Connections | |
| Analog Inputs (4): | SMA |
| Clock Input: | SMA |
| Trigger Input: | SMA |
| Sync Input: | SMA |
| Digital Input / Output: | SMA |
| Analog Inputs – Amplifier | |
| Full Scale Voltage: | 500 mV |
| Impedance: | 50 ohms |
| Bandwidth: | 1.0 MHz to 1.0 GHz (AC-Coupled) DC to 1.0 GHz (DC-Coupled) |
| SNR (dc-500 MHz): | 46 dB |
| SFDR (1-500 MHz): | 55 dB |
| Analog Inputs – Transformer | |
| Full Scale Input Voltage: | 700 mV |
| Impedance: | 50 ohms |
| Bandwidth: | 5.0 MHz to 2.0 GHz (AC-Coupled) |
| SNR (dc-500 MHz): (@ 1000 MHz): (@ 1500 MHz): |
46 dB 44 dB 42 dB |
| SFDR (5-1000 MHz): (@ 1500 MHz): |
55 dB 48 dB |
| External Trigger | |
| Signal Type: | LVPECL (3.3V Logic) |
| Impedance: | 50 ohms to +1.3V |
| Internal Synthesized Clock | |
| Frequency Range: | 200-1500 MHz |
| Resolution: | better than 62.5 PPM |
| Accuracy: | better than 5 PPM |
| External Clock | |
| Signal Type: | sine wave or square wave |
| Coupling: | AC |
| Impedance: | 50 ohms |
| Termination: | Ground or +1.3V |
| Frequency: | 200-1500 MHz |
| Amplitude: | 800 mV (-300/+1200) |
| Post ADC Clock Divider | |
| Divider Settings: | 1, 2, 4, 8, 16, 32 |
| Reference Clock | |
| Internal: | 10.0 MHz, +/- 5 ppm max. |
| External: | 10.0 MHz, +/- 50 ppm max (required for lock) |
| Digitizer | |
| Type: | ADC08D1520 (National) |
| Resolution: | 8 Bits |
| Clock Rate: | 200 – 1500 MHz |
| Digital Input / Output | |
| Type: | TTL Logic Level (standard) |
| Max. Frequency: | 200 MHz |
| Connection: | series 100 ohms to FPGA I/O |
| Trigger Modes | |
| Post Trigger: | single start trigger fills active memory |
| Pretrigger: | single trigger stops acquisition |
| Segmented: | start trigger for each memory segment |
| Trigger Options | |
| Pretrigger Samples: | 8k samples max., total all channels |
| Delayed Trigger: | 64k digitizer clock cycles max. |
| Memory | |
| Total Size: | 2 Gigasamples |
| Segment Size: | Up to 128 Megasamples |
| Segment Re-Arm Time: | 150 nanoseconds |
| Addressing: | DMA transfers from starting address |
| Power Requirements | |
| +12V: | 1.0 Amps max. |
| +3.3V: | 3.3 Amps max. |
| Absolute Maximum Ratings | |
| Analog Inputs: | +/- 3.5 volts |
| Trigger Input: | -0.2 to +4.0 volts DC |
| Clock Input: | 5 volts peak to peak |
| Operating Temperature: | +32 to +122F / 0 to +50C |
| Storage Temperature: | -4 to +158F / -20 to +70C |
| Operating Relative Humidity: | 10% to 90%, non-condensing |
| Operating Vibration: | 0.25 G, 5 Hz to 500 Hz |
| Operating Shock: | 2.5 G, 11 ms, 1/2 sine |
| Board Dimensions: | 7.5” L x 4.3” H x 0.75” W / 19.0cm L x 10.9cm H x 1.9cm W |


