PX12500A – 500 MS/s, 12 bit, AC Coupled, 2 Channel, PCIe x8, High Speed Digitizer Board
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PX12500A Features

- 2 AC-Coupled Analog Channels at up to 500 MHz Sample Rate per Channel
- 12 Bits of A/D Resolution
- Bandwidth from 100 KHz to 500 MHz
- 512 MB RAM
- 1400 MB/s Continuous Transfer Over PCI Express Bus (8 lanes)
The PX12500A is an AC-coupled dual channel waveform capture board that provides a remarkable combination of high speed and high resolution sampling along with a very large memory capacity. Signal frequencies up to 200 MHz can be accurately captured when using the programmable gain amplifier or up to 500 MHz if the direct transformer coupled connection is used.
The PX12500A has a primary sample-data RAM bank of 512 MB memory that may be used as an exceptionally large FIFO for acquiring non-stop, continuous data directly to the PCI Express (PCIe) bus. In Buffered Acquisition Mode (where the 512 MB RAM FIFO is used) the PX12500A is capable of sustaining 1400 MB/s over the PCIe bus. Significant test data has shown that recording with large FIFO buffering can be continuous at these rates even when operating in traditional non real-time environments such as the Windows operating system.
The PX12500A was designed to maximize the quality of the captured signal in terms of signal-to-noise ratio and spurious-free dynamic range over a very wide frequency range. The programmable amplifier allows for setting the full scale input voltage from 220 millivolts to 3.5 volts in 1 dB steps.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 20 to 500 MHz (except 277.5 to 308.3 MHz and 444 to 463 MHz), offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
Product Specifications
Product: PX12500A (AC-Coupled) Full Data Sheet
Update: Revision 1.02 - 04/03/2012
File Size: 619 KB
| External Signal Connections | |
| Analog Input, Channel 1: | SMA |
| Analog Input, Channel 2: | SMA |
| Clock Input: | SMA |
| Trigger Input: | SMA |
| Digital Input / Output: | SMA |
| Analog Inputs – Amplifier | |
| Full Scale Voltage Ranges: | 220 mV to 3.5 V in 1dB steps |
| Impedance: | 50 ohms |
| Bandwidth: | 100kHz - 200 MHz (Bessel filter) |
| SNR (1-200 MHz): | 61 dB |
| SFDR (@ 100 MHz): | 75 dB |
| Analog Inputs – Transformer | |
| Full Scale Voltage Ranges: | 1.1 Volts |
| Impedance: | 50 ohms |
| Bandwidth: | 500 kHz to 500 MHz |
| SNR (1-200 MHz): | 63 dB |
| SFDR (@ 100 MHz): | 77 dB |
| External Trigger | |
| Signal Type: | digital, TTL signal level |
| Impedance: | >10k ohms |
| Bandwidth: | 50 MHz |
| Internal Synthesized Clock | |
| Frequency Range: | 58.0 - 500 MHz |
| Resolution: | better than 10 PPM |
| Accuracy: | better than 5 PPM |
| Unsettable Ranges: | 277.5 - 308.3 MHz and 444 - 463 MHz |
| External Clock | |
| Signal Type: | sine wave or square wave |
| Coupling: | AC |
| Impedance: | 50 ohms |
| Frequency: | 20 MHz to 500 MHz |
| Amplitude: | 100 mV p-p to 2.0 V p-p |
| Post ADC Clock Divider | |
| Divider Settings: | 1, 2, 4, 8, 16, 32 |
| Reference Clock | |
| Internal: | 10.0 MHz, +/- 5 ppm max. |
| External: | 10.0 MHz, +/- 50 ppm max (required for lock) |
| Digital Input / Output | |
| Type: | TTL Logic Level (standard) |
| Max. Frequency: | 200 MHz |
| Connection: | 50 ohms to FPGA I/O |
| Trigger Modes | |
| Post Trigger: | single start trigger fills active memory |
| Pretrigger: | single trigger stops acquisition |
| Segmented: | start trigger for each memory segment |
| Trigger Options | |
| Pretrigger Samples: | samples prior to trigger are stored; Single Channel: 8k max.; Dual Channel: 4k max per channel |
| Delayed Trigger: | delay from trigger to data storage; Up to 64k digitizer clock cycles |
| Memory | |
| Total Size: | Up to 256 Megasamples |
| Segment Size: | Up to 128 Megasamples |
| Segment Re-Arm Time: | 150 nanoseconds |
| Addressing: | DMA transfers from starting address |
| Power Requirements | |
| +12V: | 1.0 Amps max. |
| +3.3V: | 3.3 Amps max. |
| Absolute Maximum Ratings | |
| Analog Inputs: | +/- 4 volts |
| Trigger Input: | -0.2 to +4.0 volts DC |
| Clock Input: | 5 volts peak to peak |
| Operating Temperature: | +32 to +122F / 0 to +50C |
| Storage Temperature: | -4 to +158F / -20 to +70C |
| Operating Relative Humidity: | 10% to 90%, non-condensing |
| Operating Vibration: | 0.25 G, 5 Hz to 500 Hz |
| Operating Shock: | 2.5 G, 11 ms, 1/2 sine |
| Board Dimensions: | 7.5” L x 4.3” H x 0.75” W / 19.0cm L x 10.9cm H x 1.9cm W |


